1. Field of the Invention
This invention relates to electronic systems. Specifically, the present invention relates to testing electronic systems.
2. Description of the Related Art
Scan tests are often used in digital logic designs to test the design for manufacturing defects, which result in faulty circuit behavior. For example, a microprocessor or Application Specific Integrated Circuit (ASIC) may include tens of millions of logic gates in one device. Internal scan tests are used to test the logic gates in these various devices to assure that they have been manufactured correctly.
To create these internal scan tests, an automated test pattern generator (ATPG) is employed. The ATPG is software that analyzes a model of a circuit (called a netlist), identifies a set of potential fault sites, and generates test patterns that are necessary to test the fault sites.
Storage elements (called flip-flops) on the device under test are connected serially during test operations into a scan chain. FIG. 1A displays a conventional scan chain. In FIG. 1A scan chain segments 102, 104, and 106 are connected serially and form the scan chain. Each scan chain segment 102, 104, and 106 includes flip-flops, such as flop-flops 101, 103, and 105. Lastly, a scan input data pin 100 is also shown. A test pattern is applied to the scan chain through the scan input data pin 100.
A conventional circuit includes logic gates and flip-flops connected in a scan chain. Each scan chain may contain a unique collection of flip-flops organized as a shift register during test operations. A test pattern is shifted into the scan chain serially, one bit per clock cycle. The test pattern provides an input to logic gates connected to the flip-flops comprising the scan chain. As a result, the outputs (i.e., response to the test pattern) of the logic gates are stored in the flip-flops that are part of the scan chain. As the response is shifted out of the scan chain, another test pattern is shifted into the scan chain. Each test pattern is generated with the intention of discovering faults in the logic surrounding the flip-flops in the scan chain. Therefore, the ATPG generates patterns that will place specific states in the flip-flops comprising the scan chain so that faults in the surrounding logic can be identified. For example, if there are 1000 flip-flops and a fault would be exposed when there is a logical 1 on the 3rd device in the scan chain and a logical zero on the 579th device in the scan chain, the ATPG would generate a test pattern with a logical 1 as the 3rd bit and a logical zero as the 579th bit.
Typically, every logic gate on the device is tested. Therefore, a tremendous amount of data is generated with each test pattern and a substantial amount of test patterns have to be generated to properly test a device. For example, ATPG programs may run for weeks to create test patterns for large, complex circuits.
Since the flip-flops are connected in a serial chain and each bit in the test pattern is shifted into the scan chain at the rate of one bit per clock cycle, when there are tens of millions of bits, it takes a substantial amount of time to shift the test patterns into the scan chain. The cost of performing the scan chain test is directly proportional to the amount of time required to perform the test. As a result, a number of techniques have been developed to attempt to optimize the time and lower the cost associated with scan chain testing.
One technique for lowering the cost associated with scan test involves reducing the amount of data that is shifted into the scan chain. However, shifting half of the data into the scan chain results in half of the quality in the output product and may increase rework cost and reduce profit. The devices may ship faster and incur less cost during test; however, since the quality is lower, the repair and maintenance issues increase and drive up the cost.
Another technique for lowering the cost associated with scan test is to replace a single long scan chain with several shorter scan chains that contain the same flip-flops. This allows the same total amount of scan data to be loaded and unloaded in less time. However, since each scan chain requires one pin for scan input data and another pin for scan output data, there will be an upper limit on the number of independently accessible scan chains that can be constructed.
One conventional cost reduction technique mitigates this limitation by sharing the scan input data among several short scan chains. The technique is commonly referred to as the “Illinois Scan” configuration (i.e., invented at the University of Illinois). FIG. 1B displays the “Illinois Scan” configuration. In the Illinois scan configuration, the scan chain segments that were initially connected serially (i.e., 102, 104, 106 of FIG. 1A) are now connected in parallel with a common scan input data pin 100. For illustration by comparison, using FIG. 1A, scan chain segments 102, 104, and 106 would typically be connected serially so that they are independently accessible (i.e., unique data could be loaded into each flip-flop). However, in the Illinois Scan configuration, the scan chains (102, 104, 106) are connected in parallel and the same serial bit stream is shifted into each scan chain at the same time. Therefore, as the serial bit stream is shifted into the shared scan input data pin 100, all flip-flops on parallel scan chains at a given logical distance downstream of the scan input data pin 100 will be loaded with identical data. For example, on the fourth clock cycle, the same logical bit will reside in flip-flop 101, flip-flop 103, and flip-flop 105.
Although the Illinois Scan configuration does improve on the prior art, this technique has shortcomings. For example, the same data is shifted into each scan chain. As such, the same data arrives at devices that are parallel to each other. For example, the same logical state will reside on flip-flop 101, 103, and 105. However, some faults may not be detectable unless flip-flop 101 is logical 0, flip-flop 103 is a logical 1, and flip-flop 105 is a logical 1. Since the same logical state resides on flip-flops 101, 103, and 105 in the Illinois Scan configuration, there is no way to introduce the bit pattern that will expose this fault using the Illinois Scan configuration. As a result, using the Illinois Scan configuration in this manner, it will not be possible to test the device for all possible faults (i.e., complete fault coverage).
The additional positional constraints placed on the ATPG when using the Illinois Scan configuration complicate the test generation process, and the effort expended by the ATPG to prove that such faults are untestable can be exponential in run time. Furthermore, any faults that are undetectable solely as a result of the scan configuration must be tested by other means. For example, the ATPG may reapply the test pattern with the scan chain reconfigured back to the original serial configuration (i.e., FIG. 1A).
Thus, there is a need for a more efficient scan test creation process that takes advantage of the efficiencies provided by a shared scan input data pin while minimizing the extra work in pattern creation to maintain complete fault coverage.